The inventive concepts described herein relate to nonvolatile memory devices and to method of operating the same, and more particularly, to nonvolatile flash memory devices including error correction coding (ECC) functionality and to method of operating flash memory devices including ECC functionality.
FIG. 1 schematically illustrates an example of a memory block BLK1 of a NAND flash memory cell array in which a plurality of nonvolatile memory cells are coupled at respective intersections of word lines WL<0:31> and bit lines BL<1:m>. The memory cells are connected in series to one of the bit lines BL to define a memory cell “string”, with each string commonly connected to a common source line CSL. Further, each string includes a ground select line GSL transistor and a string select line SSL transistor at opposite ends thereof. The data stored in the memory cells of each word line WL constitute a page 1111 of data. As discussed later herein, in the case of multi-level cell (MLC) memory devices, each word line WL stores multiple pages of data.
FIG. 2 is a block diagram schematically illustrating an example of a nonvolatile memory device. As shown, the nonvolatile memory 1100 includes a nonvolatile memory cell array 1110, an address decoder 1130, a data input/output (I/O) circuit 1120, and a control logic and high voltage generator 1140. The address decoder 1130 is responsive to the control logic and high voltage generator 1130 to decode a read/write address ADDR and to apply program/read voltages, etc., to selected addressed word lines WL of the nonvolatile memory cell array 1110. The data I/O circuit 1120 also responsive to the control logic and high voltage generator 1130, and includes, for example, bit line BL selection circuitry, write drivers, and read circuitry associated with the input and output of data (DATA). The control logic and high voltage generator controls an overall operation of the nonvolatile memory 1100, and generates the relative high voltages needed in programming memory cells of the memory cell array 1110. The memory cell array 1110 includes a plurality of memory blocks BLK <1:n>, such as the memory block BLK1 shown in FIG. 1.
Multi-level cell (MLC) memory devices are characterized by to programming of two (2) or more bits of stored data in each single memory cell. In the case of an N-bit MLC flash memory device (where N is a positive integer), this is accomplished by setting the threshold voltage (e.g., through Fowler-Nordheim tunneling) of each memory cell to within one of 2N threshold distributions.
FIG. 3 illustrates threshold voltage distributions in the example of a 2-bit MLC flash memory device. As shown, the threshold voltage of each memory cell is set to one of four threshold voltage distribution states, namely, an erased state E, or one of programmed states P1, P2 and P3. As also shown, the threshold voltage distribution states E, P1, P2 and P3 are assigned stored data bits of ‘11’, ‘10’, ‘00’, and ‘01’, respectively.
Generally, each bit of the MLC memory cells has a separate page address. For example, in a 2-bit MLC memory cell, the stored least significant bits (LSB) of the cells of a word line constitute a first page of data, and the stored most significant bits (MSB) of the cells of the word line constitute a second page of data. Thus, the N-bit MLC memory cells (where N is two or more) connected to a given word line stores N pages of data.
MLC memory devices have been developed in response to the demand for higher integration. However, as is apparent from FIG. 2, the gaps between threshold voltage distributions of the MLC memory cells is reduced as the number of bits (N) increases, which can have a negative impact on read margins. As such, a memory controller, which interfaces between a host and the flash memory device, may be equipped with an error correction code (ECC) circuit configured to detect and correct errors in data read from the MLC memory cells. Error probability increases in proportion to the number of data bits stored in each memory cell, and thus, the resources devoted to the complexity, size and operating time of ECC circuit can substantially increase in MLC memory devices.